Hello

Due to a PCB issue, I need INT#/CTL[15] either fixed to 0.0 V or high impedance. Currently, I did not do anything with it and it drives an intermeidate level of 1.5 V.

From the technical reference manual (Spec No.: 001-76074 Rev. *B), I learn "The INT# pin can be configured to indicate the presence of FX3 in low-power mode" so I assume that it can actually be configured. But how?

Regards
Peter

Hi,

i'm using FX3 and the AN75779 example in order to manage a couple of video sensors and to sample analog signals @32KHz using an AD converter connected to the SPI port.

I'm developing this project on CYUSB3KIT-003 board and an APTINA sensor.

Every around 30 microseconds FX3 detects the EOC syncing a MISO falling edge when SCLK doesn't run, then it writes 4 bytes to the ADC and after reads 3 bytes from it. The 4 written bytes change with each sample.

I connected MISO to GPIO45 pin on J7 socket and FX3 polls continously this pin waiting for EOC.

Several issues on this task.

I'm not using yet DMA for SPI transfer: is it possible to sync DMA byte TX & RX on the MISO falling edge, as an external inerrrupt? Maybe using external hardware in order to clean the MISO transactions due to the data transfer. Or better cleaning other pending interrupt requests to SPI DMA?

Moreover, after the detection of the EOC, may the DMA read seven bytes from a TX data buffer and in the same time write seven bytes to a RX data buffer, and then call a callback function?

I created a thread that manages the SPI communication with 8 as priority level, but i noted a great jitter (tens of milliseconds: it seems the transmission of the sensor line data) when the PC host requires the video stream from FX3: how can I avoid this jitter and guarantee the detection of an EOC every 30 microseconds and the execution of the callback?

Connecting MISO and GPIO45, the input signal coming from the ADC greatly reduces itself so i had to put an hardware buffer between MISO and GPIO45 pins. It is possible to avoid this external buffer?
 

Thanks.
Massimo

Assume I have two states with no FW_TRG connections, I want the state machine to move from one to the other. 

Is that feasible with CyU3PGpifSMSwitch? 

What will be the arbitration between CyU3PGpifSMSwitch and condition of the state machine path in the GPIF II designer diagram? 

Will CyU3PGpifSMSwitch take higher priority? 

Hello,

We have a problem of unexpected data loss (due to some FIFO FULL) when we try to use short packets.
Please note that when we are not using short packets, we have no problem and sustain easily a 350 MB/s stream.

=============  Here is a description of the system  =============
Data is provided by a FPGA (running our code)
Data goes through a FX3 embedded on a PM3 enclustra card
Data then goes to a software of our own

Software side :
  we link to the FX3 1.3.3 CyAPI library
  we use a very efficient reading on a bulk end point, using multiple-circular-scheduled async reads (BeginDataXFer()). We are pretty sure to be very efficient
  we request reads of 4MB
  all reads actually return 4MB, except when a short packet is coming. In this case, one read will return less data, but then the next reads will get 4MB againHello,

We have a problem of unexpected data loss (due to some FIFO FULL) when we try to use short packets.
Please note that when we are not using short packets, we have no problem and sustain easily a 350 MB/s stream.

=============  Here is a description of the system  =============
Data is provided by a FPGA (running our code)
Data goes through a FX3 embedded on a PM3 enclustra card
Data then goes to a software of our own

Software side :
  -we link to the FX3 1.3.3 CyAPI library
  -we use a very efficient reading on a bulk end point, using multiple-circular-scheduled async reads (BeginDataXFer()). We are pretty sure to be very efficient
  -we request reads of 4MB
  -all reads actually return 4MB, except when a short packet is coming. In this case, one read will return less data, but then the next reads will get 4MB again
  -we observe no timeouts (as expected, of course)
  -for information, we want to add short packets in the stream for future development
  
FX3 side :
  -we compile our own FX3 bootimage, based on standard slavefifo example
  -we use the auto DMA mode, with 4 DMA buffers for the channel we use, configured for infinite transfers
  -we use a standard GPIF machine (see attached screenshot)

FPGA side :
  -we emit data, and every 250ms a short packet is (correctly) emitted by pulling PKTEND low. "Correctly" means that we think to respect the documentation about the signals timings.
  
=============  Here is a description of the problem  =============
Software side :
  -several KB are missing almost every 250 ms (see below the explanation when observing the signal lines)
FX3 side :
  -nothing to say. Everything is automatic, so we do not get much information. We tried to bypass the IDLE state of the state machine by adding connections between the SHORT_PKT and the DSS_STATE, but it does not change anything.
FPGA side :
  -we observe the signal lines. Almost at every short packet (but not at every ones), the FLAGB ("dedicated thread not ready") line remains high during dozen of microseconds (which is huge). So, the FPGA fifos will get full since data is not allowed to be transferred during that time. At the rate of emission of data, this is why the software observe several KB of missing data.

See the attached screen shot :
PKEND# goes to '0' along with  the last word of data and SLWR# pulse. So the GPIF state machine interprets it as a short packet. Unfortunatly, the FLAGB signal goes to '0' after around 200µs, indicate that the dedicate thread is not ready to receive data. The FLAGB remains low during around 63 µs and the upstream fifo inside FPGA goes FULL so we loose data.

=============  Our request  =============
We need some guidance about what is going wrong, what could be done...
For information, we plan to use short packets for a special mode where the FGPA emits few data, in unpredicatable amounts. Thus, to avoid timouts and data loss on the software side, we need to use either short packets or zeo-length packets.
Thus, it is true that short packets are not needed in our current design at 350 MB/s, but, we still want it to work in that case before going further. We don't think that it should prevent that mode from working.

Why Fx3 Device was switch to EHCI Mode When it Connected to XHCI Mode?

a FX3 Device Connected to a XHCI Host controller， the most time it works fine in XHCI Mode， But some time， when i install the driver for the device； or Hot-Plugging the device and so on， the FX3 device is changed to USB2 Device(the usbdevice in device descriptor is 0x210).

But,we don't want our fx3 device using in EHCI mode,  is there any help？

thanks in advance

hello.

I use CYUSB3014. StreamerExample and USBBulkLoopAuto.

when I connect device with PC through usb3.0 and download USBBulkLoopAuto to the FX3, USB control center displays the device only work on usb2.0(including other img file provided by SDK). why this device only works on usb2.0

I need to increment an eeprom counter when a watchdog reset event occurs. I am aware that I can use a static variable in ram memory. But in that case i would not be able to distinguish between a true watchdog reset and a hardware reset (hardware reset button press event). 

Is there a way to reimplement the default watchdog interrupt handler?
Or may be there is even simpler approach to that very problem?

Thank you in advance.

Hi,

I'm new in the FX3 platform. I'm thinking about purchasing the FX3 Super Speed Explorer Kit. But First I'm trying to study all the documentation.

I want to develop a UVC with an Aptina (On Semiconductor CMOS Sensor) with parallel interface. I know there is an example with another aptina sensor but first of all I'm going to try to study the example and I would like to check how is the support.

I've followed the Application Note: AN75705_Getting_Started_with_EZ-USB_FX3.pdf after installing the Cypress EZ USB Suite and to import the Cypress SDK firmware folder but when I open the files from the project suddenly appears a lot of errors. I attach an image with the errors.

Any suggestion to solve this problem?

Best regards.

Hi,

I'm working on a project using FX3 device (CYUSB3014), which is mostly based on official slave fifo example. Now, almost every thing works fine. But there is a problem that I can't figure out why. Currently, the firmware has an U2P DMA channel used for bulking out. The DMA channel has 4 DMA buffers and each of them has length of 16384 bytes. The burst length is set to 16. The DMA channel uses U-port input socket 1 as producer socket and P-port socket 0 as consumer socket. FLAGA is bound to that DMA channel. FX3 is connected to an FPGA.

On the PC sides, I use API function XferData(buf, len) to send data to FX3. The problem is when "len" is an integral number of 1024, FLAGA is always 0 (I use SignalTap II to check FLAGA), but function XferData(buf, len) returns true, and the actual transformed length is equal to what I passed to it. However, when "len" is not an integral number of 1024, FLAGA works as expected. How could I solve this problem?

Thanks.

Hi,

I'm trying to understand how to program the FX3 in production. I've been checking the Superspeed Explorer Kit and I've seen that there is a IC with the part number CY7C65215.

In our product we are planning to have an  I2C eeprom to boot the firmware so, Is this IC  CY7C65215 necessary to program the I2C eeprom or Can you do this by the USB 3.0 connector?

Best regards.

I'm working on a Enclustra KX1 board, trying to write from the FPGA to GPIF2. Filling one buffer which according to spec should be transfered to the IN endpoint.  The Cypress device is EZ-USB FX3. I do not have exact specifications of the firmware of the fx3 but it should according to their support be a bog-standard implementation of slfifosync from the SDK.

I can't quite get the interface to work, soo I was hoping I could get some help :)

I've created a simple module to write to the slaveFIFO (see StreamIN/StreamINCore).
StreamIN is a wrapper setting all the constants, and connecting some LEDS for debugging.
StreamINCore does the actual writing to the bus.

I am able to write to the FX3 and see FLAGA be asserted. I'm guessing FLAGA means there's data to read, and FLAGB means it is not full. (FLAGB=0 => Buffer=Full). ( I can write a total of 4*512 bytes to the FX3 before OUT buffer is full ).

I find the examples from Cypress hard to use, and does not seem to work for me. (See example: slfifosync.png)
Here they simply wait for FLAGB to go low as an indication of buffer being full. 

In the(Designing with EZ-USB SlaveFifo) documentation this photo (write_seq.png) describes a write sequence, this is conflicting with the example. The example simply hardwires PKTEND although performing burst transfers. (Since waiting for FLAGB might go over several cycles). In my case I cannot see anything happening to FLAGB, thus it continues to write for eternity.

So how do I play the GPIF interface, or what am I doing wrong? 

(SystemVerilog files are saved as *.sv.txt to be able to upload)
Thanks in advance!

We are using Cypress FX3 device in our system, hooked in a self power configuration.

While making some testing on performance speed using an Ubuntu system, we are seeing some degradation with respect to a Windows based PC.

Changing power method from self-powered to bus-powered, there seems to be a slight improvement to performance on SS speeds.

Now, I have two questions:

1. Is there any correlation between power method and FX3 speed?

2. Are there any special notes when using Ubuntu, and more specifically an embedded version of it?

Refael.

Hi,

we recently switch from SDK Version 1.3.1 to 1.3.3 and found that our FX3 USB Device Application when connected at USB High Speed, each call to CyU3PUsbSendEP0Data() takes 20 ms which previously took well below 1 ms.

The device has two IN Data Endpoints (one Isochronous and one Interrupt) and we traced the problem down to a modification in the implementation of CyU3PUsbSendEP0Data()  which now makes a call to CyU3PUsbSuspendInEpChannels (), which tries to suspend all IN Endpoints before doing the DMA for Endpoint 0.

It seems the call to CyU3PDmaChannelSuspendUsbConsumer() with waitOption set to 10 always needs 10 ms to complete.

What can be done to prevent this problem? Is it really necessary to suspend Interrupt and Isochronous IN Endpoints while doing EP0 data transfers?

The Cypress EZ-USB FX3 SDK Release Notes Version 1.3.3 mentions one point: 

while the 1.3.3 firmware implementation in cyu3usb.c and cyu3channel.c suspends ALL IN endpoints, not just BULK.

Which kind of corruption can happen due to concurrent transfers?

What is the best workaround to make CyU3PUsbSendEP0Data() calls to work again as fast as before while having other IN Endpoints in an USB device? Would it be sufficient to suspend only BULK-IN endpoints?

Thanks for any help,

Peter

Hi.

I wanted to try to program the FX3 CYUSB3KIT-001 using example from Quick Start Guide. I followed all the steps and after successful programming I do not have Cypress USB StreamerExample in device manager and the Streamer does not see it too. 

If someone could help me i would be grateful.

Hi,

I used CYUSB3KIT-003 board in one my designs , it has an amplifier to amplify the antenna analog signal , an ADC to convert the signal to digital and an FPGA for managing data and send it to PC through 

CYUSB3KIT-003 board. my board and CYUSB3KIT-003 board connected through the two 2x20 connector (headers on usb3kit and pins on fpga board part). i send fpga managed data with a 100 MHz Clock (i use the asynchronous FIFO example provided in the package ) and with the rate of 260 MBytes/s.
now , the problem is that the long tracks that connects fpga outputs to the cypress usb3 chip on the CYUSB3KIT-003 (and of course the connectors) generate a huge amount of noise, and even without any amplification you can see the noise generated by the CYUSB3KIT-003 board input digital signals on the data captured by the ADC , very clearly (they have the amplitude of more than tens of milivolts ).
My question is that how i can get rid of them? (preferably without having to design a new board with the usb3 chip mounting on it )
can i resolve the problem and also use the CYUSB3KIT-003 board in the design ?

before the computer sleep ,the video stream is normal ,the mannul_force the computer into sleep ,then wake up the computer ,the video steam is stop ,the following is the log of bushound:

  20.1            USTS   c0007000                            no device          75us         1.1.0(170M)  

then i press the "reset device "button in the upload picture ,then the video stream continue.

so i can't find the reason .hope answers.

Hi~

Can I know to use CX3065 on my project.

I will use OV sensor and the image(raw 10bit) is bypassed to PC. 

I know CX3's total maximum bandwidth is 2.4Gbps.

I think I can under FPS and image sensor. 

Please check this.

1280 x 720 raw10 180fps

: 1650 x 750 x 10 x 180 = 2.2275Gbit/s

1920 x 1080 raw10 90fps

: 2200 x 1125 x 10 x 90 = 2.2275Gbit/s

If image size(included horizontal and vetical blanking)*FPS is under 2.4Gbps, can I used this chip?

have a nice day~

Working through the book "SuperSpeed Device - Design by Example", at the Ch.4 Example 7 there is mention of hooks from Cypress in regard with threads/semaphores/etc.. indicating when changes occurs, so that the Engineer can monitor with a Logic Analyzer on GPIO pins such sequences, in Real-Time.

There is a phrase in the book at pg.87: "At my request, Cypress have added an RTOS kernel hook that informs us when it starts up a new thread and when this thread suspends". Looking in the ProfileDebug's makefile of the Example 7, there is a line there that calls the gcc compiler, with parameters pointing to "...\Cypress\EZ-USB FX3 SDK\1.3\firmware/u3p_firmware/lib/fx3_profile_debug/cyu3lpp.a" (and others like that).

However, in my full-install of the FX3 SDK, in the ...firmware/u3p_firmware/lib/ folder there are just two variants of those libs: fx3_debug and fx3_release; no sign of the fx3_profile_debug !!.

From where can I get those "Profiling enabled" build of the FX3 libraries, please ?

Thank you.

Hi everyone,

I'm trying to read the i2c registers from MT9M131 CMOS sensor using the FX3 IC. I was reading the UVC_AN75779 example. But this CMOS sensor: MT9M131 is slightly different from MT9M114 used in the example UVC_AN75779:

The address size is 8 bits instead of 16 bits, so I have to change the functions SensorRead2B and SensorWrite2B.

I've started changing the fucntion SensorRead2B, but it doesn't work, so I'm not sure If I doing this issue correctly. According to the datasheet of the MT9M131, this is the scheme of a reading of 16 Bits:

START - Address (0xBA) - ACK - Address2read (For example: 0x02) - ACK - START - Address (0xBB) - ACK - Data MSB  (8 bits) - ACK - Data LSB  (8 bits) - NACK - STOP 

And this is the function I can't achieve to work well:

CyU3PReturnStatus_t SensorRead2B (
        uint8_t slaveAddr,
        uint8_t addr,
        uint8_t *buf)
{
    CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
    CyU3PI2cPreamble_t preamble;

    if ((slaveAddr != SENSOR_ADDR_RD) && (slaveAddr != I2C_MEMORY_ADDR_RD))
    {
        CyU3PDebugPrint (4, "I2C Slave address is not valid!\r\n");
        return 1;
    }

    preamble.buffer[0] = slaveAddr & I2C_SLAVEADDR_MASK;        /*  Mask out the transfer type bit. */
    preamble.buffer[1] = addr;
    preamble.buffer[2] = slaveAddr;
    preamble.length    = 3;
    preamble.ctrlMask  = 0x0004;                                /*  Send start bit after second byte of preamble. */
 

    apiRetStatus = CyU3PI2cReceiveBytes (&preamble, buf, 2, 0);
    SensorI2CAccessDelay (apiRetStatus);

    return apiRetStatus;
}

Any suggestion?

Best regards.

I'm wondering where I can find the file arm926ejs_FX3.cfg.  It looks like the most recent version of OpenOCD has the correct devices installed to work with the CY7C65215 on the Explorer Kit board.  But that I can't tell until I try.

Otherwise I'll also need the patch files to patch and recompile OpenOCD.

Any advice is welcome.

I also have the same questions for Linux.

I have no access to Windows.  Haven't touch the stuff in about 15 years. ;-)

Finally, I want to get up and running on the kit using the debugger built in through the CY7C65215 on both Mac and Linux.  Any pointers to someone who has already done this with advice would be great.

Thanx for the help in advance.